Verification Engineer

Application ends: October 20, 2023
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Job Description

We are looking for a Senior Verification Engineer to join our dynamic team.

What You Will Work On:

  • Collaborate with our dynamic team to bring innovative ideas and intricate designs to life, contributing to both new and ongoing ASIC projects.
  • Participate in ASIC projects either at modern Solna-Stockholm head office or at our customer’s offices in the Stockholm area.
  • Engage in a variety of tasks, including IP design and verification, as well as different levels of Subsystem integration and verification.
  • Work with complex ASIC and/or large FPGA designs, ensuring their functionality and performance.
  • Apply your expertise in UVM (Universal Verification Methodology) for at least one year, demonstrating proficiency in UVM verification and SystemVerilog.
  • Manage verification of IP blocks and navigate multi-clock domains.
  • Utilize RTL (Register Transfer Level) languages such as Verilog, VHDL, and/or SystemVerilog for design and verification.
  • Communicate effectively in English, both in speech and writing.

What You Bring:

  • A strong foundation in UVM verification and SystemVerilog.
  • Experience working with complex ASIC and/or large FPGA designs.
  • Previous involvement in IP block verification.
  • Proficiency in RTL using Verilog, VHDL, and/or SystemVerilog.
  • Excellent English language skills for effective communication.

Meritorious Experience:

  • Expertise in test bench structuring and design.
  • Leadership qualities, demonstrating the ability to guide and mentor others.
  • Knowledge of RTL design.
  • Scripting skills for automation.
  • Practical lab experience.
  • Experience in the telecommunications industry.

 If this sounds interesting, please send your CV to