Software Engineer/Developer

Senior ASIC Designer – 10567

Lund, Sweden

Onsite

Huy Tran

HR Administrator

cv@veritaz.se

Job Summary

Posted Date

October 7, 2024
Work Type

Onsite
Deadline

2024-10-31
Schedule

Full-time
Location

Lund, Sweden

Job Description

Assignment Description:

We are looking for a Senior ASIC Designer to join our dynamic team.

What you will work on:

Contribute to the development and design of complex ASICs and large FPGA systems.
Work with multi-clock domain environments to ensure seamless integration.
Collaborate on projects involving both new designs and the optimization of existing ASIC solutions.
Utilize System Verilog to drive development processes.
Communicate and collaborate effectively with team members to deliver high-quality results.

What you bring:

5+ years of experience in ASIC development.
Proven experience working with complex ASIC and/or large FPGA designs.
Expertise in multi-clock domain designs and handling the associated challenges.
Strong proficiency in System Verilog.
Excellent English communication skills, both written and verbal.

Meritorious if you have:

Experience in systemization and architecture design.
Knowledge of backend processes including timing constraints, timing optimization, and formal verification.
Familiarity with UVM verification methodologies.
Scripting skills for design automation.
Background in the telecom sector.

If this sounds interesting, please send your CV to cv@veritaz.se

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