Electrical/Electronics

Senior ASIC Designer – 11229

Stockholm, Sweden
Onsite

Huy Tran

HR Administrator

cv@veritaz.se

Job Summary

  • Posted Date

    January 9, 2025

  • Work Type

    Onsite

  • Deadline

    2025-01-31

  • Schedule

    Full-time

  • Location

    Stockholm, Sweden

Job Description

Assignment Description:

We are looking for a Senior ASIC Designer to join our dynamic team.

What you will work on:

  • Participate in the development of complex ASIC and large FPGA designs.
  • Work on projects involving multi-clock domains and parameterized IP block design.
  • Utilize System Verilog for ASIC development and contribute to SOC/DSP architecture design.
  • Engage in tasks related to packet-based communication protocols.
  • Collaborate effectively in teams to achieve project goals and meet customer requirements.

What you bring:

  • Over 5 years of experience in ASIC development, with a strong foundation in complex ASIC and/or large FPGA design.
  • Expertise in multi-clock domains and parameterized IP block design.
  • Proficiency in System Verilog and familiarity with SOC/DSP architecture.
  • Experience with packet-based communication protocols.
  • Strong English skills, both written and spoken.

Preferred qualifications:

  • Experience in systemization and architecture design.
  • Background in backend tasks, including timing constraints, timing optimization, and formal verification.
  • Knowledge of UVM verification and simulation tools like Xcelium.
  • Proficiency with version control systems (e.g., GIT) and linting tools (e.g., Spyglass).
  • Scripting skills in Python, shell scripting, or Tcl.
  • Experience in the telecom sector.

If this sounds interesting, please send your CV to cv@veritaz.se 

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