Senior ASIC Designer - 11382

Assignment Description:

We are looking for a Senior ASIC Designer to join our dynamic team.

What you will work on:

Contribute to the development of complex ASIC and large FPGA designs.
Work with multi-clock domain systems and parameterized IP block designs.
Design and implement using SystemVerilog for SOC/DSP architectures.
Engage in projects involving packet-based communication protocols.
Collaborate on ASIC systemization and architecture design.
Support backend tasks such as timing constraints, optimization, and formal verification.
Utilize simulation tools (e.g., Xcelium) and verification frameworks (e.g., UVM).
Leverage tools like GIT and linting tools (e.g., Spyglass) for development and quality assurance.

What you bring:

Over 4 years of experience in ASIC development with a strong technical foundation.
Proficiency in designing complex ASICs and/or large FPGA systems.
Expertise in multi-clock domains and SystemVerilog.
Strong understanding of SOC/DSP architecture and packet-based communication protocols.
Fluency in English, both written and spoken.
Familiarity with scripting languages such as Python, shell scripts, or Tcl.

Meritorious skills:

Experience in systemization and architectural design.
Hands-on experience with UVM verification and simulation tools like Xcelium.
Proficiency in backend processes, including timing constraints and optimization.
Knowledge of telecom systems and processes.

If this sounds interesting, please send your CV to cv@veritaz.se

Senior ASIC Designer – 11382