Software Engineer/Developer

Senior ASIC Verifier – 10566

Stockholm, Sweden
Onsite

Huy Tran

HR Administrator

cv@veritaz.se

Job Summary

  • Posted Date

    October 7, 2024

  • Work Type

    Onsite

  • Deadline

    2024-10-31

  • Schedule

    Full-time

  • Location

    Stockholm, Sweden

Job Description

Assignment Description:

We are looking for a Senior ASIC Verifier to join our dynamic team.

What you will work on:

  • Perform verification of complex ASIC designs, focusing on both new projects and the enhancement of existing ones.
  • Utilize UVM and SystemVerilog to verify IP blocks and ensure the integrity of multi-clock domain systems.
  • Collaborate closely with the design teams to execute comprehensive verification plans for large FPGA and ASIC projects.
  • Engage in IP block verification processes, ensuring high-quality outcomes.

What you bring:

  • 6+ years of experience in ASIC verification.
  • 2+ years of hands-on experience with UVM methodology.
  • Strong expertise in UVM verification and SystemVerilog.
  • Proven experience working with complex ASIC and/or large FPGA designs.
  • Familiarity with IP block verification and multi-clock domains.
  • Proficient English communication skills, both written and spoken.

Meritorious if you have:

  • Experience in test bench structuring and design.
  • Knowledge of RTL design.
  • Scripting skills for test automation.
  • Lab experience for hands-on verification tasks.
  • Experience in the telecom sector.

If this sounds interesting, please send your CV to cv@veritaz.se

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