Software Engineer/Developer

Senior UVM Verification Engineer

Stockholm, Sweden
Onsite

Huy Tran

HR Administrator

cv@veritaz.se

Job Summary

  • Posted Date

    September 12, 2025

  • Work Type

    Onsite

  • Deadline

    2025-09-26

  • Schedule

    Full-time

  • Location

    Stockholm, Sweden

Job Description

Assignment Description:

We are looking for a Senior UVM Verification Engineer to join our dynamic team.

What you will work on:

  • Develop and execute UVM-based testbenches for complex digital designs.
  • Create and maintain verification plans, test cases, and coverage metrics.
  • Collaborate with design engineers to interpret specifications and resolve issues.
  • Analyze simulation results, document findings, and present them to design and verification teams.
  • Drive continuous improvements in verification methodologies, tools, and workflows.

What you bring:

  • Strong hands-on experience with UVM (Universal Verification Methodology).
  • Proficiency in SystemVerilog and digital verification concepts.
  • Practical experience with industry-standard simulation tools (Mentor, Cadence, Synopsys).
  • Bachelor’s or Master’s degree in Electronics, Computer Engineering, or related field.
  • Strong teamwork, problem-solving, and communication skills.

Nice to have:

  • Experience with coverage-driven verification.
  • Familiarity with Python, Perl, or TCL for scripting and automation.

If this sounds interesting, please send your CV to cv@veritaz.se 

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