Software Engineer/Developer
Senior UVM Verification Engineer
Stockholm, Sweden
Onsite
Job Summary
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Posted Date
September 12, 2025
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Work Type
Onsite
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Deadline
2025-09-26
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Schedule
Full-time
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Location
Stockholm, Sweden
Job Description
This post is also available in: Svenska (Swedish)
Assignment Description:
We are looking for a Senior UVM Verification Engineer to join our dynamic team.
What you will work on:
- Develop and execute UVM-based testbenches for complex digital designs.
- Create and maintain verification plans, test cases, and coverage metrics.
- Collaborate with design engineers to interpret specifications and resolve issues.
- Analyze simulation results, document findings, and present them to design and verification teams.
- Drive continuous improvements in verification methodologies, tools, and workflows.
What you bring:
- Strong hands-on experience with UVM (Universal Verification Methodology).
- Proficiency in SystemVerilog and digital verification concepts.
- Practical experience with industry-standard simulation tools (Mentor, Cadence, Synopsys).
- Bachelor’s or Master’s degree in Electronics, Computer Engineering, or related field.
- Strong teamwork, problem-solving, and communication skills.
Nice to have:
- Experience with coverage-driven verification.
- Familiarity with Python, Perl, or TCL for scripting and automation.
If this sounds interesting, please send your CV to cv@veritaz.se
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