Electrical/Electronics

Senior Verification Engineer – 12301

Stockholm, Sweden
Onsite

Huy Tran

HR Administrator

cv@veritaz.se

Job Summary

  • Posted Date

    April 23, 2025

  • Work Type

    Onsite

  • Deadline

    2025-05-12

  • Schedule

    Full-time

  • Location

    Stockholm, Sweden

Job Description

Assignment Description:

We are looking for a Senior Verification Engineer to join our dynamic team.

What you will work on:

  • Participate in ASIC verification activities across multiple projects
  • Collaborate in teams handling IP design and subsystem integration/verification
  • Apply UVM methodology for verification of complex ASIC or large FPGA designs
  • Perform IP block verification, including modules with multiple clock domains
  • Contribute to developing and maintaining robust test benches

What you bring:

  • Minimum 5 years of experience in ASIC verification
  • Strong knowledge of UVM and SystemVerilog
  • Proven experience with complex ASIC and/or large FPGA systems
  • Background in verifying IP blocks with multi-clock domain considerations
  • Excellent English communication skills, both written and verbal
  • Familiarity with AXI5 and ACE5 protocols (meritorious)
  • Experience using Cadence tools, particularly Xcelium (meritorious)
  • Understanding of test bench architecture and structure (meritorious)
  • Leadership skills and ability to guide peers (meritorious)
  • Knowledge of RTL design principles (meritorious)
  • Scripting skills for automation (meritorious)
  • Exposure to the telecom domain (meritorious)

.If this sounds interesting, please send your CV to cv@veritaz.se 

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